Volumetric Degenerative Routing for 3D Network-On-Chip
As we reach the limits of scaling down of circuits, Three Dimensional Integrated Circuits (3D ICs) offer a very promising opportunity to keep on increasing the processing capacities and speed. In a Multi-Processor System-on-Chip (MPSoC) based embedded system with Network-on-chip (NOC) as the communi...
| Main Author: | |
|---|---|
| Format: | Others |
| Published: |
North Dakota State University
2018
|
| Online Access: | https://hdl.handle.net/10365/27297 |