Formal Verification Methodology for Asynchronous Sleep Convention Logic Circuits Based on Equivalence Verification
Sleep Convention Logic (SCL) is an emerging ultra-low power Quasi-Delay Insensitive (QDI) asynchronous design paradigm with enormous potential for industrial applications. Design validation is a critical concern before commercialization. Unlike other QDI paradigms, such as NULL Convention Logic (NCL...
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| Format: | Others |
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North Dakota State University
2020
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| Online Access: | https://hdl.handle.net/10365/31574 |