Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer

Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer

Approved for public release, distribution is unlimited === This thesis outlines the development, programming, and testing a logical interface between a radar system, the AN/SPS-65(V)1, and a general-purpose reconfigurable computing platform, the SRC Computer, Inc. model, the SRC-6E. To confirm the p...

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Bibliographic Details
Main Author: Guthrie, Thomas G.
Other Authors: Fouts, Douglas J.
Format: Others
Published: Monterey California. Naval Postgraduate School Marc
Subjects:
Radar transmitters
Signal processing
Computer hardware description languages
VHDL (Computer hardware description language)
C programming
Field programmable logic device (FPLA)
Hardware description language (HDL)
Programmable logic device (PLD)
Radar
Reconfigurable computing
VHDL
Online Access:http://hdl.handle.net/10945/2287

Internet

http://hdl.handle.net/10945/2287

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