Design of a pipelined multiplier using a Silicon Compiler
Approved for public release; distribution is unlimited. === This thesis describes the design methodology and the process of employing the GENESIL Silicon Compiler (GSC)(Version 7.1) in the layout of a pipelined multiplier, in 1.5 micron CMOS technology, using a parallel multiplier cell array. Additi...
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Monterey, California: Naval Postgraduate School
2013
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| Online Access: | http://hdl.handle.net/10945/27760 |