VLSI design for pipelined FFT processors
A system of custom cell building blocks utilizing scaleable CMOS technology is decribed. The cells are design to support the high speed, pipelined addition, subtraction, and multiplication operations neccessary in a cyclic spectral analyser or other applications involving the FFT. The cells are stru...
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| Language: | en_US |
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Monterey, California: Naval Postgraduate School
2013
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| Online Access: | http://hdl.handle.net/10945/28644 |