Analog preprocessing in a SNS 2 [mu] low-noise CMOS folding ADC
Significant research in high performance analog-to-digital converters (ADCs) has been directed at retaining part of the high-speed flash ADC architecture, while reducing the total number of comparators in the circuit. The symmetrical number system (SNS) can be used to preprocess the analog input sig...
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| Language: | en_US |
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Monterey, California. Naval Postgraduate School
2013
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| Online Access: | http://hdl.handle.net/10945/30531 |