Design of a synchronous pipelined multiplier and analysis of clock skew in high-speed digital systems
Approved for public release; distribution is unlimited === Digital systems implemented with high-speed transistor technologies face a variety of design challenges in an effort to keep pace with the accelerating demand for performance. As device switching frequencies climb comfortably into the gigahe...
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| Language: | en_US |
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Monterey, California. Naval Postgraduate School
2012
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| Online Access: | http://hdl.handle.net/10945/7670 |