Performance Analysis of a Hierarchical, Cache-Coherent, Shared Memory Based, Multi-processor System

Performance Analysis of a Hierarchical, Cache-Coherent, Shared Memory Based, Multi-processor System

We have conducted a performance analysis of a large scale multiprocessor system based on shared buses organized in a hierarchical fashion and employing an easy to implement snoopy cache protocol. · This arrangement, named TREEBUS [ 5], presents a logical extension path for multiprocessor systems bas...

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Bibliographic Details
Main Author: Nayyar, Raman
Format: Others
Published: PDXScholar 1993
Subjects:
Computer architecture > Mathematical models
Computer storage devices > Mathematical models
Parallel processing (Electronic computers) > Mathematical models
Electrical and Computer Engineering
Online Access:https://pdxscholar.library.pdx.edu/open_access_etds/4695
https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=5766&context=open_access_etds

Internet

https://pdxscholar.library.pdx.edu/open_access_etds/4695
https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=5766&context=open_access_etds

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