Minimization of Sum-of-Conditional-Decoders Structures with Applications in Finite Machine EPLD Design and Machine Learning

Minimization of Sum-of-Conditional-Decoders Structures with Applications in Finite Machine EPLD Design and Machine Learning

In order to achieve superior speed in sequencer designs over competing PLD devices, Cypress brought to market an innovative architecture, CY7C361. This architecture introduced a new kind of universal logic gate, the CONDITION DECODER (CDEC). Because there are only 32 macrocells in the chip, saving o...

Full description

Bibliographic Details
Main Author: Mohamedsadakathulla, Sanof
Format: Others
Published: PDXScholar 1995
Subjects:
Computer algorithms
Electrical and Computer Engineering
Online Access:https://pdxscholar.library.pdx.edu/open_access_etds/5158
https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=6230&context=open_access_etds

Internet

https://pdxscholar.library.pdx.edu/open_access_etds/5158
https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=6230&context=open_access_etds

Similar Items