Minimization of Sum-of-Conditional-Decoders Structures with Applications in Finite Machine EPLD Design and Machine Learning
In order to achieve superior speed in sequencer designs over competing PLD devices, Cypress brought to market an innovative architecture, CY7C361. This architecture introduced a new kind of universal logic gate, the CONDITION DECODER (CDEC). Because there are only 32 macrocells in the chip, saving o...
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Format: | Others |
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PDXScholar
1995
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Online Access: | https://pdxscholar.library.pdx.edu/open_access_etds/5158 https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=6230&context=open_access_etds |