Methodologies for Test and Diagnosis of Delay Defects in Integrated Circuits

• Main Author: Mysore somashekar, Ahish
• Format: Others
• Published: OpenSIUC 2015
• Online Access: https://opensiuc.lib.siu.edu/dissertations/1117; https://opensiuc.lib.siu.edu/cgi/viewcontent.cgi?article=2121&context=dissertations

The failure of devices due to timing-related defects is becoming increasingly prominent in the nanometer era, thereby causing quality and reliability concerns. The variations in physical parameters and the increasing influence of environmental factors are the potential sources of such timing-related defects. In this dissertation we present novel techniques for detection and diagnosis of such timing-related defects, in particular small delay defects, in modern integrated circuits. First, an approach capable of identifying the locations of distributed small delay defects, arising due to manufacturing aberrations, is proposed. It is shown that the proposed formulation can be transformed into a Boolean Satisfiability form to be solved by any SAT solver. The approach is capable of providing a small number of alternative sets of defective segments. One of the solutions is the actual defect configuration. This is shown to be a very important property towards the effective identification of the defective segments. Experimental analysis on ISCAS and ITC benchmark suites show that the proposed approach is highly scalable and identifies the location of multiple delay defects. Second, a Monte Carlo based approach is proposed capable of identifying in a path-implicit and scalable manner the distributions that describe the delay of every path in a combinational circuit. Furthermore, a scalable approach to select critical paths from a potentially exponential number of path candidates is presented. Paths and their delay distributions are stored in Zero Suppressed Binary Decision Diagrams. Experimental results on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed method is highly scalable and effective. Lastly, an approach to select a set of longest (highest critical) paths under a probabilistic delay model is presented. It is shown how to select a set of top critical paths that need to be tested for a given test margin and subsequently, it is shown how one can select critical paths to effectively test a device for small delay defects that may occur due to undesirable process shifts in different pockets of the device. Experimental analysis compares the proposed approach to recent approaches in the literature that claim to select critical paths for testing and merits both based on their effectiveness in detecting random delay defects in the device under test.