HIGH LEVEL SYNTHSIS FOR A NETWORK ON CHIP TOPOLOGY
Network on chips (NoCs) have emerged as a panacea to solve many intercommunication issues that are imposed by the fast growing of VLSI design. NOC have been deployed as a solution for the communication delay between cores, area overhead, power consumption, etc. One of the leading parameters of speed...
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| Format: | Others |
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OpenSIUC
2013
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| Online Access: | https://opensiuc.lib.siu.edu/theses/1079 https://opensiuc.lib.siu.edu/cgi/viewcontent.cgi?article=2090&context=theses |