Accelerated Successive Approximation Technique for Analog to Digital Converter Design
This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary...
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| Format: | Others |
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OpenSIUC
2015
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| Online Access: | https://opensiuc.lib.siu.edu/theses/1630 https://opensiuc.lib.siu.edu/cgi/viewcontent.cgi?article=2644&context=theses |