Exploiting level sensitive latches in wire pipelining

The present research presents procedures for exploitation of level sensitive latches in wire pipelining. The user gives a Steiner tree, having a signal source and set of destination or sinks, and the location in rectangular plane, capacitive load and required arrival time at each of the destinations...

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Bibliographic Details
Main Author: Seth, Vikram
Other Authors: Hu, Jiang
Format: Others
Language:en_US
Published: Texas A&M University 2005
Subjects:
Online Access:http://hdl.handle.net/1969.1/1433