Clock tree synthesis for prescribed skew specifications
In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in determining circuit performance including timing, power consumption, cost, power supply noise and tolerance to process variations. It is required that a clock layout algorithm can achieve any prescribe...
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| Format: | Others |
| Language: | en_US |
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Texas A&M University
2005
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| Online Access: | http://hdl.handle.net/1969.1/2212 |