Statistical static timing analysis considering process variations and crosstalk
Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die variations have become dominant and it is imperative to model them to obtain accurate timing analy...
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| Format: | Others |
| Language: | en_US |
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Texas A&M University
2005
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| Online Access: | http://hdl.handle.net/1969.1/2545 |