Design, Implementation and Evaluation of a Configurable NoC for AcENoCs FPGA Accelerated Emulation Platform

Design, Implementation and Evaluation of a Configurable NoC for AcENoCs FPGA Accelerated Emulation Platform

The heterogenous nature and the demand for extensive parallel processing in modern applications have resulted in widespread use of Multicore System-on-Chip (SoC) architectures. The emerging Network-on-Chip (NoC) architecture provides an energy-efficient and scalable communication solution for Multic...

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Bibliographic Details
Main Author: Lotlikar, Swapnil Subhash
Other Authors: Gratz, Paul V.
Format: Others
Language:en_US
Published: 2011
Subjects:
FPGA
NoC
Network-on-Chip
On-Chip Communication
SoC
System-on-Chip
RTL
HDL
Hardware Description Language
Hardware-Software Emulation Framework
Network-on-Chip Emulation
Network-on-Chip Validation
Network-on-Chip Design Space Exploration
Online Access:http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8381

Internet

http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8381

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