Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips
Dr. Paul V. Gratz Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8457 |