Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor
In nanometer technologies, process variation control and low power have emerged as the first order design goal after high performance. Process variations cause high variability in performance and power consumption of an IC, which affects the overall yield. Short channel effects (SCEs) deteriorate th...
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| Format: | Others |
| Language: | en_US |
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2011
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| Online Access: | http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488 |