An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization
Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common method for handling multi-objectives and proven to reach optimal solution unde...
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| Format: | Others |
| Language: | en_US |
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2012
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| Online Access: | http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8684 |