Built-In Self Test (BIST) for Realistic Delay Defects

Built-In Self Test (BIST) for Realistic Delay Defects

Testing of delay defects is necessary in deep submicron (DSM) technologies. High coverage delay tests produced by automatic test pattern generation (ATPG) can be applied during wafer and package tests, but are difficult to apply during the board test, due to limited chip access. Delay testing at the...

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Bibliographic Details
Main Author: Tamilarasan, Karthik Prabhu
Other Authors: Walker, Duncan M.
Format: Others
Language:en_US
Published: 2012
Subjects:
Delay test
small delay defects
weighted random pattern generation
Online Access:http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8923
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spelling ndltd-tamu.edu-oai-repository.tamu.edu-1969.1-ETD-TAMU-2010-12-89232013-01-08T10:42:49ZBuilt-In Self Test (BIST) for Realistic Delay DefectsTamilarasan, Karthik PrabhuDelay testsmall delay defectsweighted random pattern generationTesting of delay defects is necessary in deep submicron (DSM) technologies. High coverage delay tests produced by automatic test pattern generation (ATPG) can be applied during wafer and package tests, but are difficult to apply during the board test, due to limited chip access. Delay testing at the board level is increasingly important to diagnose failures caused by supply noise or temperature in the board environment. An alternative to ATPG is the built-in self test (BIST). In combination with the insertion of test points, BIST is able to achieve high coverage of stuck-at and transition faults. The quality of BIST patterns on small delay defects is an open question. In this work we analyze the application of BIST to small delay defects using resistive short and open models in order to estimate the coverage and correlate the coverage to traditional delay fault models.Walker, Duncan M.Choi, Gwan2012-02-14T22:18:53Z2012-02-16T16:13:39Z2012-02-14T22:18:53Z2012-02-16T16:13:39Z2010-122012-02-14December 2010thesistextapplication/pdfhttp://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8923en_US
collection NDLTD
language en_US
format Others
sources NDLTD
topic Delay test
small delay defects
weighted random pattern generation
spellingShingle Delay test
small delay defects
weighted random pattern generation
Tamilarasan, Karthik Prabhu
Built-In Self Test (BIST) for Realistic Delay Defects
description Testing of delay defects is necessary in deep submicron (DSM) technologies. High coverage delay tests produced by automatic test pattern generation (ATPG) can be applied during wafer and package tests, but are difficult to apply during the board test, due to limited chip access. Delay testing at the board level is increasingly important to diagnose failures caused by supply noise or temperature in the board environment. An alternative to ATPG is the built-in self test (BIST). In combination with the insertion of test points, BIST is able to achieve high coverage of stuck-at and transition faults. The quality of BIST patterns on small delay defects is an open question. In this work we analyze the application of BIST to small delay defects using resistive short and open models in order to estimate the coverage and correlate the coverage to traditional delay fault models.
author2 Walker, Duncan M.
author_facet Walker, Duncan M.
Tamilarasan, Karthik Prabhu
author Tamilarasan, Karthik Prabhu
author_sort Tamilarasan, Karthik Prabhu
title Built-In Self Test (BIST) for Realistic Delay Defects
title_short Built-In Self Test (BIST) for Realistic Delay Defects
title_full Built-In Self Test (BIST) for Realistic Delay Defects
title_fullStr Built-In Self Test (BIST) for Realistic Delay Defects
title_full_unstemmed Built-In Self Test (BIST) for Realistic Delay Defects
title_sort built-in self test (bist) for realistic delay defects
publishDate 2012
url http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8923
work_keys_str_mv AT tamilarasankarthikprabhu builtinselftestbistforrealisticdelaydefects
_version_ 1716505133157711872

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