STT-MRAM Based NoC Buffer Design
As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory - STT MRAM (Spin-Torque Transfer Magnetic RAM) which provides substantial power and area savings, near zero leak...
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| Format: | Others |
| Language: | en_US |
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2012
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| Online Access: | http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684 |