A verilog-hdl implementation of virtual channels in a network-on-chip router
As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC) implementa...
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| Format: | Others |
| Language: | en_US |
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2010
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| Online Access: | http://hdl.handle.net/1969.1/ETD-TAMU-2890 http://hdl.handle.net/1969.1/ETD-TAMU-2890 |