An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design
In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimizat...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | English |
| Published: |
University of North Texas
1993
|
| Subjects: | |
| Online Access: | https://digital.library.unt.edu/ark:/67531/metadc500878/ |