Power reduction of a CMOS high speed interface using Clock Gating

Power reduction of a CMOS high speed interface using Clock Gating

Bibliographic Details
Main Author: Nelson Tiago Lopes da Silva
Other Authors: Faculdade de Engenharia
Format: Others
Language:English
Published: 2019
Subjects:
Ciências da engenharia e tecnologias
Engineering and technology
Online Access:https://repositorio-aberto.up.pt/handle/10216/68024

Internet

https://repositorio-aberto.up.pt/handle/10216/68024

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