System-level design of power efficient FSMD architectures

System-level design of power efficient FSMD architectures

Power dissipation in CMOS circuits is of growing concern as the computational requirements of portable, battery operated devices increases. The ability to easily develop application specific circuits, rather than program general-purpose architectures can provide tremendous power savings. To this end...

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Bibliographic Details
Main Author: Agarwal, Nainesh
Other Authors: Dimopoulos, Nikitas J.
Language:English
en
Published: 2009
Subjects:
System-Level
VLSI
Power
CAD
FSMD
Hardware
High-level synthesis
clock gating
power gating
partitioning
CoDeL
Simulated Annealing
ILP
ESL
UVic Subject Index::Sciences and Engineering::Engineering::Electrical engineering
UVic Subject Index::Sciences and Engineering::Applied Sciences::Computer science
Online Access:http://hdl.handle.net/1828/1405

Internet

http://hdl.handle.net/1828/1405

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