A 12-b 50Msample/s Pipeline Analog to Digital Converter
This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the...
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Digital WPI
2000
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| Online Access: | https://digitalcommons.wpi.edu/etd-theses/749 https://digitalcommons.wpi.edu/cgi/viewcontent.cgi?article=1748&context=etd-theses |