Reduction of Parasitic Capacitance in Vertical MOSFETs by Spacer Local Oxidation
Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their oayout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned p...
| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
2003-06.
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| Subjects: | |
| Online Access: | Get fulltext |