Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems
A dynamic voltage scaling (DVS) technique for embedded systems expressed as conditional task graphs (CTGs) is described. The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also the effect of combining a genetic algorithm ba...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
2003-09.
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| Subjects: | |
| Online Access: | Get fulltext |