Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs
A simple process is described for the fabrication of a shallow drain junction on a pillar sidewall in sub-100nm vertical MOSFETs. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The dept...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
2006.
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| Subjects: | |
| Online Access: | Get fulltext Get fulltext |
| LEADER | 01298 am a22002053u 4500 | ||
|---|---|---|---|
| 001 | 263281 | ||
| 042 | |a dc | ||
| 100 | 1 | 0 | |a Gili, E. |e author |
| 700 | 1 | 0 | |a Uchino, T. |e author |
| 700 | 1 | 0 | |a Hakim, M.M.A. |e author |
| 700 | 1 | 0 | |a de Groot, C.H. |e author |
| 700 | 1 | 0 | |a Buiu, O. |e author |
| 700 | 1 | 0 | |a Hall, S. |e author |
| 700 | 1 | 0 | |a Ashburn, Peter |e author |
| 245 | 0 | 0 | |a Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs |
| 260 | |c 2006. | ||
| 856 | |z Get fulltext |u https://eprints.soton.ac.uk/263281/1/2006EnricoDPPaperEDL.pdf | ||
| 856 | |z Get fulltext |u https://eprints.soton.ac.uk/263281/2/shallow.pdf | ||
| 520 | |a A simple process is described for the fabrication of a shallow drain junction on a pillar sidewall in sub-100nm vertical MOSFETs. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible, and hence facilitates the integration of a sub-100nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a sub-threshold slope of 95mV/dec (at VDS =1V) and a DIBL of 0.12V. | ||
| 655 | 7 | |a Article | |