Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs
A simple process is described for the fabrication of a shallow drain junction on a pillar sidewall in sub-100nm vertical MOSFETs. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The dept...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
2006.
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| Subjects: | |
| Online Access: | Get fulltext Get fulltext |