A VLSI Array Architecture for Realization of DFT, DHT, DCT and DST
A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (CoOrdinate Rotation DIgital Computer) arithmetic unit as the basic Processing Element (PE). All these four transforms can be computed by simple rearrangement of input samples. Compared to five...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
2001.
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| Subjects: | |
| Online Access: | Get fulltext |