Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems
In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
2008-03.
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| Subjects: | |
| Online Access: | Get fulltext |