Fault Tolerance Techniques for Hybrid CMOS/Nano Architecture
We propose two fault tolerance techniques for hybrid CMOS/nano architecture implementing logic functions as Look-Up Tables. We compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both pro...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
2009-08-27.
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| Subjects: | |
| Online Access: | Get fulltext |