VLSI implementation of a 2.8 Gevent/s packet based AER interface with routing and event sorting functionality

VLSI implementation of a 2.8 Gevent/s packet based AER interface with routing and event sorting functionality

State-of-the-art large scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an FPGA-ma...

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Bibliographic Details
Main Authors: Stefan eScholze, Stefan eSchiefer, Johannes ePartzsch, Stephan eHartmann, Christian Georg Mayr, Sebastian eHöppner, Holger eEisenreich, Stephan eHenker, Bernhard eVogginger, Rene eSchüffny
Format: Article
Language:English
Published: Frontiers Media S.A. 2011-10-01
Series:Frontiers in Neuroscience
Subjects:
configurable pulse delays
configuration over AER
packet based AER
serial AER in VLSI
Online Access:http://journal.frontiersin.org/Journal/10.3389/fnins.2011.00117/full

Internet

http://journal.frontiersin.org/Journal/10.3389/fnins.2011.00117/full

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