A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC

A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC

This article presents an accurate quadrature phase-locked loop (PLL) with quadrature phase mismatch calibration for 32 GS/s analog-to-digital converter (ADC). Due to the mismatches of clock distribution in layout and variations of the active devices, the quadrature phase of the sampling clock is sig...

Full description

Bibliographic Details
Main Authors: Shunli Ma, Tianxiang Wu, Junyan Ren
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Phase locked loop (PLL)
quadrature phase
jitter
phase noise
quadrature divider
time-interleaved sampling
Online Access:https://ieeexplore.ieee.org/document/9286446/

Internet

https://ieeexplore.ieee.org/document/9286446/

Similar Items