A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS

A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS

This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digital-to-analog converter (CDAC) structure is adopted for reducing the core area and improving the sampling spe...

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Bibliographic Details
Main Authors: Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Successive approximation register (SAR) analog-to-digital converter (ADC)
CMOS
split-CDAC
customized unit capacitor
asynchronous logic
figure-of-merit (FoM)
Online Access:https://ieeexplore.ieee.org/document/9429217/

Internet

https://ieeexplore.ieee.org/document/9429217/

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