Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology

Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology

Different Half-Bridge (HB) converter topologies for an Integrated Voltage Regulator (IVR), which serves as a microprocessor application, were evaluated. The HB circuits were implemented with Stacked Transistors (HBSTs) in a cutting-edge 14 nm CMOS technology node in order to enable the integration o...

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Bibliographic Details
Main Authors: Pedro André Martins Bezerra, Florian Krismer, Johann Walter Kolar, Riduan Khaddam-Aljameh, Stephan Paredes, Ralph Heller, Thomas Brunschwiler, Pier Andrea Francese, Thomas Morf, Marcel André Kossel, Matthias Braendli
Format: Article
Language:English
Published: MDPI AG 2021-05-01
Series:Electronics
Subjects:
IVR
CMOS
stacked transistors
half-bridge
multi-phase
14 nm technology
Online Access:https://www.mdpi.com/2079-9292/10/10/1150

Internet

https://www.mdpi.com/2079-9292/10/10/1150

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