A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time Delta Sigma ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 mu m CMOS
The use of a VCO-based integrator and quantizer within a continuous-time (CT) \Delta \Sigma analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 \mum CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1....
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| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers,
2010-05-11T14:20:39Z.
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| Subjects: | |
| Online Access: | Get fulltext |