Photonic integration in a commercial scaled bulk-CMOS process

Photonic integration in a commercial scaled bulk-CMOS process

We demonstrate the first photonic chip designed for a commercial bulk CMOS process (65 nm-node) using standard process layers combined with post-processing, enabling dense photonic integration with high-performance microprocessor electronics.

Bibliographic Details
Main Authors: Kaertner, Franz X. (Contributor), Orcutt, Jason Scott (Contributor), Khilo, Anatol M. (Contributor), Popovic, M. A. (Contributor), Holzwarth, Charles W. (Contributor), Li, Hanqing (Contributor), Sun, J. (Contributor), Moss, Benjamin Roy (Contributor), Dahlem, Marcus Vinicius Sobral (Contributor), Ippen, Erich P. (Contributor), Hoyt, Judy L. (Contributor), Stojanovic, Vladimir Marko (Contributor), Smith, Henry Ignatius (Contributor), Ram, Rajeev J. (Contributor)
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor), Massachusetts Institute of Technology. Research Laboratory of Electronics (Contributor)
Format: Article
Language:English
Published: Institute of Electrical and Electronics Engineers, 2010-12-02T19:38:19Z.
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