Logic characteristics of 40 nm thin-channel InAs HEMTs
We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of t[subscript ch] = 5 nm and we h...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE),
2012-08-03T15:56:59Z.
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| Subjects: | |
| Online Access: | Get fulltext |