Massively parallelizing the RRT and the RRT*

In recent years, the growth of the computational power available in the Central Processing Units (CPUs) of consumer computers has tapered significantly. At the same time, growth in the computational power available in the Graphics Processing Units (GPUs) has remained strong. Algorithms that can be i...

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Bibliographic Details
Main Authors: Karaman, Sertac (Contributor), Frazzoli, Emilio (Contributor), Bialkowski, Joshua John (Contributor)
Other Authors: Massachusetts Institute of Technology. Department of Aeronautics and Astronautics (Contributor), Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor)
Format: Article
Language:English
Published: Institute of Electrical and Electronics Engineers (IEEE), 2013-10-21T14:44:56Z.
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Online Access:Get fulltext
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042 |a dc 
100 1 0 |a Karaman, Sertac  |e author 
100 1 0 |a Massachusetts Institute of Technology. Department of Aeronautics and Astronautics  |e contributor 
100 1 0 |a Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science  |e contributor 
100 1 0 |a Bialkowski, Joshua John  |e contributor 
100 1 0 |a Karaman, Sertac  |e contributor 
100 1 0 |a Frazzoli, Emilio  |e contributor 
700 1 0 |a Frazzoli, Emilio  |e author 
700 1 0 |a Bialkowski, Joshua John  |e author 
245 0 0 |a Massively parallelizing the RRT and the RRT* 
260 |b Institute of Electrical and Electronics Engineers (IEEE),   |c 2013-10-21T14:44:56Z. 
856 |z Get fulltext  |u http://hdl.handle.net/1721.1/81448 
520 |a In recent years, the growth of the computational power available in the Central Processing Units (CPUs) of consumer computers has tapered significantly. At the same time, growth in the computational power available in the Graphics Processing Units (GPUs) has remained strong. Algorithms that can be implemented on GPUs today are not only limited to graphics processing, but include scientific computation and beyond. This paper is concerned with massively parallel implementations of incremental sampling-based robot motion planning algorithms, namely the widely-used Rapidly-exploring Random Tree (RRT) algorithm and its asymptotically-optimal counterpart called RRT*. We demonstrate an example implementation of RRT and RRT* motion-planning algorithm for a high-dimensional robotic manipulator that takes advantage of an NVidia CUDA-enabled GPU. We focus on parallelizing the collision-checking procedure, which is generally recognized as the computationally expensive component of sampling-based motion planning algorithms. Our experimental results indicate significant speedup when compared to CPU implementations, leading to practical algorithms for optimal motion planning in high-dimensional configuration spaces. 
546 |a en_US 
655 7 |a Article 
773 |t Proceedings of the 2011 IEEE/RSJ International Conference on Intelligent Robots and Systems