A Partial Scan Design for Sequential Circuits Based on Test Generation
碩士 === 國立交通大學 === 電子研究所 === 81 === The partial scan design methodology has been recognized as a cost-efficient technique to improve the testability of sequential circuits. In this thesis, a flip-flop's value oriented partial scan appro...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1993
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| Online Access: | http://ndltd.ncl.edu.tw/handle/07235385557862305580 |