Reducing Test Cost of Sequential Machines with Lower Hardware Overhead
碩士 === 國立中興大學 === 資訊科學研究所 === 82 === Testing cost of a pure sequential machine can be reduced through a proper synthesis procedure, which modifies the functional specification of the original finite state machine (FSM). Previous works on this topic only dealt with the testability; no attempts wer...
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| Format: | Others |
| Language: | zh-TW |
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1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/52881577187808168378 |