Reducing Test Cost of Sequential Machines with Lower Hardware Overhead

• Main Author: 王啟信
• Other Authors: 王行健
• Format: Others
• Language: zh-TW
• Published: 1994
• Online Access: http://ndltd.ncl.edu.tw/handle/52881577187808168378

碩士 === 國立中興大學 === 資訊科學研究所 === 82 === 　　Testing cost of a pure sequential machine can be reduced through a proper synthesis procedure, which modifies the functional specification of the original finite state machine (FSM). Previous works on this topic only dealt with the testability; no attempts were made to reduce the final circuit size. In this thesis, we address the problem of the input assignment for modified finite state machines (MFSM), targeted towards multi-level combinational logic and feedback register implementation. We propose a method that tries to maximize the number and size of common cubes that can be found from the original FSM. A sequential machine synthesized with the proposed method needs extra hardware (in some cases it even gives smaller circuit than the original one), while at the same time the testing cost is reduced. This result can be combined with previous methods on fully testable sequential circuits to synthesize fully and easily testable sequential machines, and it should be useful to design testable VLSI sequential circuits.