| Summary: | 碩士 === 國立中興大學 === 資訊科學研究所 === 87 === Recently, integration of system into a chip becomes very popular. In testing of highly integrated chip, one difficult problem is embedded memory testing. It is hard to test embedded memory because direct controllability and observability are extremely low. To solve this problem, Built-In Self Test (BIST) technique is widely used in embedded memory testing.
Pseudo-random (PR) memory tests are tests which have the capability to detect any fault (defect) of any model, albeit with some probability less than 100%; the fault coverage is modular and depends on the test time, which makes them very attractive.
In this paper we describe a new method to improve the explicit memory test with word operations (DADWRD). By complement the written data, we could increase the probability of the detection. For the more, we modify the Markov chain of DADWRD to suitable our new algorithm. We prove that new method could reduce the test length coefficients, and the increase of area overhead is small.
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