Built-In Self Test Circuit Design for SDRAM
碩士 === 國立成功大學 === 電機工程學系 === 88 === In this thesis, we propose a march algorithm based Built-In Self Test design for Synchronous DRAM. This design can automatically generate all the commands, addresses and data to test a memory through an easy-to-control start signal. Two test methods are...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/80972317347417237842 |