| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 88 === In this thesis, we propose a march algorithm based Built-In Self Test design for Synchronous DRAM. This design can automatically generate all the commands, addresses and data to test a memory through an easy-to-control start signal. Two test methods are supported in our design. One is to use the embedded march algorithm such that the external control can be minimized. The other is via a series-in interface such that a user can scan in any required march algorithm very easily.
In addition to the flexibility in selecting the test algorithm, this BIST design uses the checker board format data background to ensure good fault coverage and uses the interleave bank access of the SDRAM to save the test time. The area of the BIST circuitry is very small compared to the size of SDRAM and the timing impact to the normal operation is also small. This design can run at 340MHz clock frequency, which is much higher than the operation frequency of any SDRAM used in industry today.
Our design can be delivered in a soft intellecture property (IP) format. An automatic IP generator has been developed such that the user can simply use a WWW browser to connect to our server through the Internet so as to generate the design files of his required BIST circuitry. With these design files, he can embed the BIST circuitry into his system and verify the whole system very easily.
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