Low Power Testing for CMOS Logic Testing
博士 === 國立成功大學 === 電機工程學系 === 90 === The increasing transistor density and operating speed in the system-on-a-chip (SOC) era make the power dissipation during test a critical issue. This dissertation proposes four techniques to reduce the power dissipation in test application time for CMOS...
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| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/23446931835307075746 |