Universal BIST for Heterogeneous Embedded Synchronous Memory cores in SOC
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === Due to the drastic growing up and heterogeneity of embedded memory cores in SOCs, the memory testing issue has become a major problem in the SOC testing. For low cost and testability consideration, BIST is a widely accepted methodology for testing embedded mem...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/yed7t2 |