| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === Due to the drastic growing up and heterogeneity of embedded memory cores in SOCs, the memory testing issue has become a major problem in the SOC testing. For low cost and testability consideration, BIST is a widely accepted methodology for testing embedded memories within SOCs. In this thesis, we propose a universal BIST design for the heterogeneous embedded memory cores in an SOC. The memory cores considered include Sync-SRAM, SDRAM, DDR SDRAM and Sync-Flash.
Because the memory cells can be tested in a regular address order, the March algorithms are popular to test the embedded memory cores of the SOC and stand-alone memories. In our design, we first propose a Universal Test Instruction Generator. We analyze the properties of March algorithms and use an efficient procedure to reduce the memory storage for these characteristics. The proposed approach integrates 42 existing march algorithms into an embedded test instruction generator. This generator is capable of executing any March algorithm with small area overhead. To deal with word-oriented memory cores, we also use a “background” signal to select different data backgrounds for memory cells. Besides, to test manifold memory cores in an SOC, different test command sequences are necessary. A mixed-type test vector generator and a command generator are proposed to generate the command sequences. According to this proposed design, the user can test heterogeneous memory cores in an SOC using a single BIST controller and hence can significantly reduce the BIST hardware overhead.
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